DDR Verification Engineer - Technical Lead

Company: CareerArc
Location: Santa Clara
Posted on: March 20, 2025

Job Description:

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.THE ROLE:We are looking for an experienced DDR Verification Expert to join our team as a Technical Lead for cutting-edge server SOC. This individual will be responsible for driving the formal verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess expert-level knowledge of formal verification tools and flows; jaspergold, vcformal, questa formal in addition to working experience in SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl, and will have a proven track record of multiple tape-out experiences and successful verification signoffs.THE PERSON:You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings and executive briefings. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.KEY RESPONSIBILITIES:

• Technical Leadership & Project Oversight: Lead and guide a team of verification engineers in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems in server products.
• Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
• Work cross-functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
• Knowledge sharing and other contributions to verification methodology.
• As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests.
• Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs.
• Support post-Si teams for Product Performance, Power and functional issues debug/resolution.PREFERRED EXPERIENCE:
  • Required experience in Formal Verification methods, with proven record of tool usage beyond the standard apps.
  • Experience in Verification sign-off using formal verification methods - preferred.
  • Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
  • Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase.
  • Provided technical leadership across multiple teams, driving cross-functional collaboration to solve complex issues in memory systems, from firmware to hardware.
  • Built VIPs and BFMs for memory interfaces from scratch is preferred.
  • GLS, NLP, XPROP simulation experience is preferred.
  • Strong proficiency in SystemVerilog assertions, constraints and coverage.
  • Excellent communication, management, and presentation skills.
  • Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies.ACADEMIC CREDENTIALS:
    • Bachelor's or Master's degree in related discipline preferred.LOCATION: Santa Clara, CA (open to AMD North America sites)
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Keywords: CareerArc, Santa Clara , DDR Verification Engineer - Technical Lead, IT / Software / Systems , Santa Clara, California