ASIC Design Engineer - Memory Cache Controller

Company: Apple Inc.
Location: Santa Clara
Posted on: November 13, 2024

Job Description:

ASIC Design Engineer - Memory Cache Controller Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth.In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy Description Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis.Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team.Develop/debug RTL design of different sections of the cache.Work with physical design team to close timing of the same. Key Qualifications

• Development of memory systems.
• Experience in PPA (performance/power/area) analysis.
• Knowledge of dedication coherent memory system or interconnect architectures.
• Strong cache design background including good understanding of different memory organizations and tradeoffs.
• Knowledge of dedication memory subsystem and dram controller.
• Hands on Experience with multi-processor cache coherence protocols Education & Experience Bachelors Degree + 10 Years of Experience.
  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.
    
    Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
    
    Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
    Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
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Keywords: Apple Inc., Santa Clara , ASIC Design Engineer - Memory Cache Controller, Engineering , Santa Clara, California